Siemens’ longstanding and deep engagement with the RISC-V community dates back to the foundation’s early days. Involved initially as the independent company UltraSoC, now as Siemens EDA, Siemens has ...

As the RISC-V ecosystem continues to grow, the need for robust verification and debug solutions remains increasingly important. However, the time, effort and cost of debugging and optimizing software ...

SiFive Insight combines trace and debug capabilities to offer a comprehensive portfolio that enables faster and easier product development. SiFive has invested heavily in SiFive Insight’s trace ...

Sipeed’s new LicheeRV is a tiny computer-on-a-module featuring a 64-bit RISC-V processor, 512MB of RAM, a microSD card for storage and a USB-C port for power and/or debugging. While the tiny computer ...

As monolithic device scaling continues to wind down and evolve toward increasingly heterogeneous designs, it has created an inflection point for chip architects to create customized cores that are ...

Adoption of RISC-V processors is accelerating. This technology, like everything, comes with benefits and risks. The open standard means freedom for many developers, but success depends on the ...

Sipeed’s LM4A compute module is a small board with a T-Head TH1520 RISC-V processor, an NPU with up to 4 TOPS of AI performance, and support for up to 16GB of LPDDR4X memory and 128GB of eMMC storage.

2025年7月17日，第五届RISC-V中国峰会在上海张江科学会堂隆重召开。作为全球三大RISC-V峰会之一和中国规模最大的RISC-V年度盛会，本次峰会吸引了众多业界领袖和专家学者共聚一堂。来自政府、产业、学术界的数千名代表和与会嘉宾围绕“开放、协同、落地”主题 ...

In context: RISC-V provides an open standard instruction set architecture (ISA) derived from RISC, a potential alternative to Arm and x86 CPUs for powering new hardware devices and low-cost ...